A Many-Core Energy and Latency Estimator

Author(s)

Ononiwu, G. C , Chukwudebe, G. A , Ndinechi, M. C , Okafor, E. N. C ,

Download Full PDF Pages: 14-23 | Views: 959 | Downloads: 231 | DOI: 10.5281/zenodo.3408066

Volume 2 - April 2013 (04)

Abstract

Many-core processors can now be used as an alternative hardware platform for implementing embedded media devices. However, a lack of generic tools for application development may hamper their rate of adoption by industry. This work has contributed towards the solution by providing an abstraction from the many design constraints facing application developers. A Many-core Energy and Latency Estimator (MELE) has been designed to improve the programmer’s ability to iteratively map data flow applications to a target machine. A set of models included in the tool transforms an application mapped to an abstract machine into its Intermediate Representation. An Abstract Interpreter which runs on the Ptolemy II modeling platform is used to return feedback from the Intermediate Representation to the programmer. A case study has been used to showcase the use of MELE in analyzing the mapping of data flow applications. The case study has also been used to explain how a rank based system can arrive at the most suitable mapping of an application to the processor based on energy and latency costs. Results from the case study shows that the use of a greater number of cores in the processing does not necessarily result in the highest ranked mapping. Also, some mappings take too long to arrive at their steady state processing cost value. This may result in a lower Quality of Service (QOS) for the application. Based on these findings, suggestions have been made for further work. 

Keywords

Many-core, Energy, Latency, Hardware, Ranking

References

  1. Dally, W. J., Balfour, J., Black-Shaffer, D., Chen, J., Harting, C. R., Parikh, V., Park, J., and Sheffield, D. (2008). Efficient Embedded Computing. IEEE Computer, July, pp 27-32.
  2. Lee, E. A. and Messershmitt, D. G. (1987). Static Scheduling of Synchronous Data Flow Programs for Signal Processing. IEEE Transactions on Computers, Vol. C – 36, No. 1, January
  3. Ononiwu, G. C., Chukwudebe, G. A., Ndinechi, M. C., Okafor, E. N. C., Opara, F. K. (2013). Models for DSP applications on tiled Many-Core Architectures. Asian Journal of Natural and Applied Sciences, ISSN: 2186-8476, Vol 2. No. 1. Pp 70-81.
  4. Thoziyoor, S., Ahn, J., Monchiero, M., Brockman, J., and Jouppi, N. (2008). A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies.In the Proceedings of the International symposium on Computer Architecture (ISCA).
  5. Brooks, D., Tiwari, V., and Martonosi, M. (2000). Wattch: a framework for architectural-level power analysis and optimizations. In the Proceedings of the International symposium on Computer Architecture (ISCA), June
  6. Kahng, A., Li, B., Peh, L. –S., and Samadi, K. (2009). ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration. DATE.
  7. Li, S., Ahn, J. H., Strong, R. D., Brockman, J. B., Tullsen, D. M., Jouppi, N. P. (2009). McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. MICRO 2009.
  8. Bengtsson, J., and Svensson, B. (2009). Manycore Performance Analysis using Timed Configuration Graphs. In the Proceedings of the international Symposium on Systems, Architectures, Modeling and Simulation (SAMOS IX 2009), Samos, Greece.
  9. International Technology Roadmap for Semiconductors, ―International technology roadmap for semiconductors—System drivers,‖ 2007 [Online]. http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_System-Drivers.pdf

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